120 research outputs found
RRAM variability and its mitigation schemes
Emerging technologies such as RRAMs are attracting significant attention due to their tempting characteristics such as high scalability, CMOS compatibility and non-volatility to replace the current conventional memories. However, critical causes of hardware reliability failures, such as process variation due to their nano-scale structure have gained considerable importance for acceptable memory yields. Such vulnerabilities make it essential to investigate new robust design strategies at the circuit system level. In this paper we have analyzed the RRAM variability phenomenon, its impact and variation tolerant techniques at the circuit level. Finally a variation-monitoring circuit is presented that discerns the reliable memory cells affected by process variability.Peer ReviewedPostprint (author's final draft
Configurable Operational Amplifier Architectures Based on Oxide Resistive RAMs
International audienceThis paper introduces memristor-based operational amplifiers in which semiconductor resistors are suppressed and replaced by memristors. The ability of the memristive elements to hold several resistance states is exploited to design programmable closed-loop operational amplifiers. An inverting operational amplifier, an integrator and a differentiator are studied. Such designs are developed based on a calibrated memristor model, and offer dynamic configurability to realize different gains and corner frequencies at reduced chip area
Public-Key Based Authentication Architecture for IoT Devices Using PUF
Nowadays, Internet of Things (IoT) is a trending topic in the computing
world. Notably, IoT devices have strict design requirements and are often
referred to as constrained devices. Therefore, security techniques and
primitives that are lightweight are more suitable for such devices, e.g.,
Static Random-Access Memory (SRAM) Physical Unclonable Functions (PUFs) and
Elliptic Curve Cryptography (ECC). SRAM PUF is an intrinsic security primitive
that is seeing widespread adoption in the IoT segment. ECC is a public-key
algorithm technique that has been gaining popularity among constrained IoT
devices. The popularity is due to using significantly smaller operands when
compared to other public-key techniques such as RSA (Rivest Shamir Adleman).
This paper shows the design, development, and evaluation of an
application-specific secure communication architecture based on SRAM PUF
technology and ECC for constrained IoT devices. More specifically, it
introduces an Elliptic Curve Diffie-Hellman (ECDH) public-key based
cryptographic protocol that utilizes PUF-derived keys as the root-of-trust for
silicon authentication. Also, it proposes a design of a modular hardware
architecture that supports the protocol. Finally, to analyze the practicality
as well as the feasibility of the proposed protocol, we demonstrate the
solution by prototyping and verifying a protocol variant on the commercial
Xilinx Zynq-7000 APSoC device
An In-Memory Architecture for High-Performance Long-Read Pre-Alignment Filtering
With the recent move towards sequencing of accurate long reads, finding
solutions that support efficient analysis of these reads becomes more
necessary. The long execution time required for sequence alignment of long
reads negatively affects genomic studies relying on sequence alignment.
Although pre-alignment filtering as an extra step before alignment was recently
introduced to mitigate sequence alignment for short reads, these filters do not
work as efficiently for long reads. Moreover, even with efficient pre-alignment
filters, the overall end-to-end (i.e., filtering + original alignment)
execution time of alignment for long reads remains high, while the filtering
step is now a major portion of the end-to-end execution time.
Our paper makes three contributions. First, it identifies data movement of
sequences between memory units and computing units as the main source of
inefficiency for pre-alignment filters of long reads. This is because although
filters reject many of these long sequencing pairs before they get to the
alignment stage, they still require a huge cost regarding time and energy
consumption for the large data transferred between memory and processor.
Second, this paper introduces an adaptation of a short-read pre-alignment
filtering algorithm suitable for long reads. We call this LongGeneGuardian.
Finally, it presents Filter-Fuse as an architecture that supports
LongGeneGuardian inside the memory. FilterFuse exploits the
Computation-In-Memory computing paradigm, eliminating the cost of data movement
in LongGeneGuardian.
Our evaluations show that FilterFuse improves the execution time of filtering
by 120.47x for long reads compared to State-of-the-Art (SoTA) filter,
SneakySnake. FilterFuse also improves the end-to-end execution time of sequence
alignment by up to 49.14x and 5207.63x compared to SneakySnake with SoTA
aligner and only SoTA aligner, respectively
Impact of Magnetic Coupling and Density on STT-MRAM Performance
As a unique mechanism for MRAMs, magnetic coupling needs to be accounted for
when designing memory arrays. This paper models both intra- and inter-cell
magnetic coupling analytically for STT-MRAMs and investigates their impact on
the write performance and retention of MTJ devices, which are the data-storing
elements of STT-MRAMs. We present magnetic measurement data of MTJ devices with
diameters ranging from 35nm to 175nm, which we use to calibrate our intra-cell
magnetic coupling model. Subsequently, we extrapolate this model to study
inter-cell magnetic coupling in memory arrays. We propose the inter-cell
magnetic coupling factor Psi to indicate coupling strength. Our simulation
results show that Psi=2% maximizes the array density under the constraint that
the magnetic coupling has negligible impact on the device's performance. Higher
array densities show significant variations in average switching time,
especially at low switching voltages, caused by inter-cell magnetic coupling,
and dependent on the data pattern in the cell's neighborhood. We also observe a
marginal degradation of the data retention time under the influence of
inter-cell magnetic coupling
Test Cost Analysis for 3D Die-to-Wafer Stacking
The industry is preparing itself for three-dimensional stacked ICs (3D-SICs); a technology that promises hetero-geneous integration with higher performance and lower power dissipation at a smaller footprint. Several 3D stacking approaches are under development. From a yield point of view, Die-to-Wafer (D2W) stacking seems the most favorable approach, due to the ability of Known Good Die stacking. Minimizing the test cost for such a stacking approach is a challenging task. Every manufactured chip has to be tested, and any tiny test saving per 3D-SIC impacts the overall cost, especially in high-volume produc-tion. This paper establishes a cost model for D2W SICs and investigates the impact of the test cost for different test flows. It first introduces a framework covering different test flows for 3D D2W ICs. Subsequently, it proposes a test cost model to estimate the impact of the test flow on the overall 3D-SIC cost. Our simulation results show that (a) test flows with pre-bond testing significantly reduce the overall cost, (b) a cheaper test flow does not necessary result in lower overall cost, (c) test flows with intermediate tests (performed during the stacking process) pay off, (d) the most cost-effective test flow consists of pre-bond tests and strongly depends on the stack yield; hence, adapting the test according the stack yield is the best approach to use
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